That's because your declaration for Q was not in the right e below I re-wrote the program again with the signal in there and REG replaced by Q but i am getting an error (Line 43: Syntax error near 'signal'.) If you tried to set 'Q <= REG' inside the process, then there would be an extra clock cycle delay that would probably not be desired. Note: With REG as a variable, you wouldn't be able to set the Q output outside of the process. Here you define what REG should be set to when it is reset Here you add your code for computing REG as a Signal REG: std_logic_vector (3 downto 0) Besides the sensitivity list, then you'll need to add code to support RST (as well as the other inputs) like this. If RST had been a synchronous reset, then RST would not be in the sensitivity list. The process will also need to have RST in the sensitivity list since the description says that RST is an asynchronous reset input. S1 and S0 are listed in the definition so why wouldn't you need them?
i also have (s0 s1) as inputs but i am not sure if i am supposed to incule them and how Variable: REG: std_logic_vector (3 downto 0) You're missing S1 and S0 inputs.add themĪrchitecture Behavioral of universal_shift_register is Port ( SIR, SIL, CLK, RST, : in STD_LOGIC I have made a start to it but i dnt know if i am on the right track.
